Design Verification Engineer

Design Verification Engineer / DV Lead\nContract\nFully Remote\n£50-60 per hour\nWe are looking for strong Individual Contributors who can work autonomously within complex verification environments while collaborating effectively across wider engineering teams.\nThis is a high-priority contract opportunity focused on complex next-generation verification projects involving PCIe, DDR/LPDDR, Ethernet, CXL and AMBA technologies within advanced HPC environments.\nThe Role\nYou will be responsible for developing and executing verification environments for high-performance controller technologies, contributing across the full verification lifecycle from planning through to debug and closure.\nKey responsibilities include:\n * Developing UVM/SystemVerilog based verification environments\n * Creating and executing new verification test cases from scratch\n * Verification of complex HPC protocols and controllers\n * Debugging complex verification issues independently\n * Working with protocol VIPs and advanced verification flows\n * Supporting coverage closure and verification sign-off activities\n * Collaborating with wider design and verification teams\nRequired Experience\n * Minimum 8 years’ Design Verification experience\n * Strong UVM and SystemVerilog expertise\n * Experience verifying one or more of:\n * PCIe\n * CXL\n * DDR/LPDDR\n * High-Speed Ethernet\n * AMBA peripherals\n * Strong debugging and problem-solving capability\n * Experience using protocol VIPs\n * Ability to work independently within fast-paced engineering programmes\nDesirable\n * Experience within HPC or advanced semiconductor environments\n * Previous work on controller verification projects\n * DV Lead experience beneficial\nPlease send your latest CV for immediate consideration